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The problem statement, all variables and given/known data My homework is to design a Serial Adder in Verilog using a shift register module, a full. ’ is not ' (notice the shape difference). Verilog works with the apostrophe character ( ', ASCII 0x27). Your ’ is likely an extended ASCII character. There is also a » character, which I believe should be! I'm guessing you wrote your code in word editor (ex Microsoft Word, LibreOffice Writer, Apple iWork, etc). These kinds of editors tend to swap ' for ’ while you type because it is more visually appealing for humans.

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Email clients and some messaging apps tend to do this too. You should always write your code in a plain texted editor or an editor intended for writing code. Emacs and Vim are popular editors for writing code; syntax highlighting plugins are available for both.

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An IDE, like Eclipse, is another option. Notepad does work as well. I also noticed you used and assign statement on the reg type temp. This is not legal in verilog. Assign statements can only be done on net types (e.g. You may have other compiling errors that will show up after fixing ’ and », the error message will likely be more helpful.

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